ATPG Driven Logic Synthesis for Area and Power Minimization
نویسندگان
چکیده
In this paper we present the application of our ATPGbased design rewiring approach to multi-level combinational logic circuit optimization. At every step of this optimization procedure, we introduce a design error by removing the logic that violates the optimization constraint(s) and then we attempt to correct the design by modifying the logic somewhere else. We give heuristics and describe the application of this method to delay optimization and to design for low power. Experiments are also presented to support the potential of our method. Ivor Ting Andreas Veneris Magdy S. Abadir Alcatel University of Toronto Motorola 4190 Still Creek Drive Dept ECE and CS 7700 W. Parmer Burnaby, BC V5C 6C6 Toronto, ON M5S 3G4 Austin, TX 78729 [email protected] [email protected] [email protected]
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